1. Field of the Invention
The present invention relates to a microprocessor which is capable of processing a variable-length instruction set and which decodes a plurality of instructions in parallel.
2. Description of the Prior Art
In any prior-art microprocessor capable of processing a variable-length instruction set, the parallel decode of instructions is not performed.
As a known example pertinent to the present invention, there is mentioned an instruction decoding method stated in a treatise "32-bit microprocessor V80 wherein the disturbance of a pipeline is suppressed by building in a cache and a branch prediction mechanism, etc., thereby to enhance a performance" contained on pp. 195-206 in NIKKEI ELECTRONICS BOOKS "New-Generation Microprocessors RISC, CISC, TRON" published on Sep. 11, 1989.
In the known microprocessor, a plurality of instructions are not really decoded in parallel, but an instruction is decoded in two stages, thereby to enhance the throughput of decode capability. The first-stage decode circuit of this known microprocessor is called a pre-decode unit, which has the function of decomposing a variable-length instruction into elements of fixed length. The instruction decomposed into the fixed-length elements in this manner is once stored in a buffer (register) within the pre-decode unit, and it is transferred from the pre-decode unit to an instruction decode unit in compliance with the request of the instruction decode unit.
Meanwhile, the official gazette of Japanese Patent Application Laid-open No. 244233/1988 discloses a microprocessor which is intended to shorten the decode time period of a variable-length machine language by decoding a plurality of unit instructions in parallel. With the microprocessor, the machine language instructions of 2 bytes are accepted from outside each time, and the unit instruction of the first byte and that of the second byte are respectively decoded by a first decoder and a second decoder. A first selector selects one decoded result from among a plurality of decoded results delivered from the first decoder. A second selector selects one decoded result from among a plurality of decoded results delivered from the second decoder, in accordance with the decode information delivered from the first selector. The select operation of the first selector is determined in accordance with the decode information delivered from the second selector. According to the microprocessor thus constructed, the machine language instructions of 2 bytes can be decoded in one machine cycle, and the decode time period of the variable-length instruction can be shortened.